The present invention relates to high speed transmission systems and more particularly to an improved 2-stage large bandwidth amplifier with diodes in the parallel feedback structure.
In high speed transmission systems such as those involved in the forthcoming 10 Gb/s Ethernet, the signal after transmission along a media is largely attenuated and needs to be amplified before any operation is performed in the receiving section (A/D conversion, clock synchronization, data serialization, . . . etc.). The amplification circuits of these systems must work at the highest possible speed because bits are serialized in the emitting section before they are sent on a single transmission channel. As a result, bandwidth and gain constraints are imposed to the amplification circuits on the receiving side of these high speed transmission systems.
Conventional amplification solutions are based on bipolar devices that are superior to MOSFET devices because of their higher Ft (transition frequency). The traditional tradeoff between gain and bandwidth usually requires multiple cascaded stages of amplifying bipolar transistors mounted in common emitter and connected in series with a resistive load on the collector of the output transistor. A known refinement is to place a parallel feedback structure from one stage to the preceding one, as shown in FIG. 1.
Now turning to FIG. 1, there is shown such a conventional amplifier referenced 10 that is comprised of two stages simply formed by two bipolar transistors Q1 and Q2 for the sake of simplicity that are connected in series. The collector of transistor Q1 is connected to the base of transistor Q2. The input signal Vin is applied to the base of in put transistor Q1 via input terminal 11, while the output signal Vout is available at output terminal 12 connected to the collector of the output transistor Q2. The parallel feedback structure 13 consists of a voltage divider comprised of resistors R1 and R2 and a bipolar transistor Q3, referred to as the feedback transistor, configured in emitter follower, that is connected in series with a load resistor Rf. Feedback transistor Q3 injects the feedback signal Vf through said resistor Rf at node 14 to the connecting node of transistors Q1 and Q2, that is referenced 15. The voltage at this node 15 is referenced Vc. In normal operation, when the feedback structure is implemented, nodes 14 and 15 are merged and voltages Vf and Vc are identical, this distinction is only worth when the feedback structure 13 is made inoperative, e.g. by cutting the wire between nodes 14 and 15 (as it will be explained later on in due course). Amplifier 10 is biased between a positive voltage Vcc and the ground Gnd. A similar circuit is described in the article “High-Bit-rate, High-In-put-Sensitivity Decision Circuit Using Si Bipolar Technology” by K. Ishii et al, IEEE Journal of Solid-State Circuits, vol 29, No 5, May 1994.
This parallel feedback structure is useful because it reduces the collector-base capacitance of input transistor Q1, which is the cause of the bandwidth roll-off at high frequencies. Nevertheless, the overall bandwidth of amplifier 10 is still limited by the second stage, i.e. Output transistor Q2, because the collector capacitance of transistor Q2 remains large. Moreover, the gain of transistor Q2 is strongly related to the value of resistors R1 and R2 and to its transconductance which vary independently of one another. Finally, amplifier 10 is often unstable, because the gain of feedback structure 13 is quite often greater than 1.